Glossary¶

A¶

AMBA¶

Principally an ARM term, Advanced Microcontroller Bus Architecture (AMBA) for the connection and management of functional blocks in a System-on-Chip (SoC).

AXI¶

Principally an ARM term, Advanced eXtensible Interface. There is also the AXI Coherency Extensions (ACE)

B¶

Beat¶

A beat is the smallest single unit of data transfer within an AXI transaction. Its size is determined by the bus width. A Burst can be comprised of multiple beats. See the Arm Glossary

BIOS¶

Basic Input/Output System.

BPF¶

Berkeley Packet Filter.

BPF Counter¶

An option on perf stat where a BPF program reads counters to a BPF map rather than the regular read of a perf event file descriptor. The BPF program
reads the counter on context switches from an event in system wide mode. If the number of system wide per CPU events is less than the number of threads
or cgroups, this option can reduce file descriptor overhead.

C¶

C2C¶

Cache-to-cache. perf c2c is a builtin perf tool for analyzing shared data accesses and problems like (false sharing)[#false-sharing].

CAKE¶

Coherent AMD socKet Extender

CCD¶

Principally an AMD term, Core Complex Dies are usually part of a CCX.

CCX¶

Prinicpally an AMD term, Core CompleX where dies are connected and share the L3 cache.

CHA¶

Principally an Intel term for Caching and Home Agent (CHA).

CHI¶

Principally an ARM term for the AMBA bus Coherent Hub Interface

CMN¶

Principally an ARM term for Coherenet Mesh Network.

Core¶

Used to refer to events on the CPU's PMU, contrast with Uncore and Offcore.
Part of the topology containing multiple SMT threads.

CPUID¶

On Intel an instruction that identifies the type and properties of the CPU. ARM64 CPUs are generally identified from /sys/devices/system/cpu/cpu0/regs/identification/midr_el1.

D¶

DSB¶

In modern Intel CPUs, the DSB (Decoded Stream Buffer) is a uop cache storing pre-decoded instructions in the form of micro-operations (uops). The DSB allows the CPU to bypass the decoding stage for frequently used instructions sequences.

DTG¶

Termed used with Marvell CN10K chips, Lookaside Translation Group used for regular virtual to physical memory management.

E¶

Events¶

The list of measurable events is supported by the perf tool.

Event Selector¶

See evsel.

evlist¶

A perf command to list the events within a perf.data file.
A list of event selectors. The evlist API is part of libperf.

evsel¶

An event selector describes a perf event that will be opened on multiple CPUs or threads. The evsel API is part of libperf.

F¶

When a cache line is accidentally shared, and written-to, by two threads because of the layout of data being so that it is on the same cache line.

Flexible Event¶

The default kind of event that can be multiplexed, contrast with pinned event.

Free Running Counter¶

A counter that runs through its full range of values before repeating.

G¶

GMI¶

AMD Global Memory Interconnect.

H¶

HITM¶

A load that Hit a Modified cacheline.

Hwmon¶

The Linux Hardware Monitoring kernel API.

Hyperthread¶

Intel/x86 term for SMT.

I¶

IBS¶

AMD Instruction-Based Sampling (IBS) allows precise a hardware performance monitoring similar to Intel PEBS. Unlike Intel PEBS, IBS provides separate PMUs to gather relevant data.

IDQ¶

The IDQ (Instruction Decode Queue) serves as a buffer between the instruction fetch/decode stages and the rest of the out-of-order execution engine in modern CPUs. It stores decoded instructions often in the form of micro-ops.

J¶

JEClear¶

Jump Execution Clear is a kind of pipeline flush on Intel CPUs cause by branch misprediction. Article on branching in Intel CPUs.

JSON¶

JavaScript Object Notation.

K¶

KVM¶

KVM stands for Kernel-based Virtual Machine, perf command with kvm helps us to trace/measure kvm guest os

L¶

L[12][DI]¶

Level 1 or 2, data or instruction cache.

Legacy Events¶

Perf events are identified by a type and a config value. The type identifies the PMU. To determine the config value, data is read from sysfs or embedded in the perf tool via json files - the appropriate json file data is identified via a cpuid. Initially all hardware events had a single type and the mapping of the event to the config value was hard coded. To allow extension, sysfs and json encodings were added. Legacy events fail in heterogeneous systems as typically a different core/CPU PMU is needed for each type of event. As users expect event event names/encodings to behave in certain ways, the removal of legacy events has proven contentious.

LFB¶

The Line Fill Buffer is a small, temporary buffer that sits between different levels of a CPU's cache (e.g., between L1 and L2). Its purpose is to speed up data access when the CPU needs data not found in the fastest cache level (a cache miss). Instead of making the CPU wait for an entire cache line to transfer from slower memory, the LFB stores the first chunk of data, allowing the CPU to start working immediately.

LSD¶

The Loop Stream Detector is a frontend component within Intel CPUs designed to boost performance for tight loops. It detects loops in code, pre-decodes their instructions, and stores these decoded micro-ops (uops) in a dedicated buffer. By feeding these uops directly to the execution engine, the LSD bypasses the slower instruction fetch and decode stages for loops, resulting in speedups.

LLC¶

The Last Level Cache (LLC) before accessing memory, generally level 3. Will generally have its own PMU

LTG¶

Termed used with Marvell CN10K chips, Lookaside Translation Group used for special virtual to physical memory management.

M¶

Metric¶

Taking multiple performance counters, typically in perf stat, and then computing a human meaningful value like memory bandwidth.

MITE¶

The Micro-instruction Translation Engine is a legacy component within modern CPUs that acts as a secondary, simpler instruction decoder. While the primary decoder handles most instructions efficiently, the MITE is responsible for decoding specific complex instructions or instruction sequences that aren't well-suited for the main decoder. The MITE often works alongside the microcode sequencer to break down these complex instructions into simpler micro-operations for the CPU to execute.

MPAM¶

Principally an ARM term for Memory System Resource Partitioning and Monitoring.

MPKI¶

Cache, TLB or branch Misses Per Kilo (1,000) Instructions.

MS¶

The microcode sequencer is a specialized unit that handles the execution of complex instructions not directly supported as a single hardware operation. It breaks down these instructions into sequences of simpler micro-operations (microcode) that the CPU's execution units can directly understand.

Multiplexing¶

When the number of events is greater than the hardware counters the kernel will multiplex the events. Each event is scheduled for a period of time (by default 1kHz) and then rotated.

O¶

Offcore¶

Devices and buses outside of the core CPU.

Off-CPU¶

Off-CPU is data collected when a task gets context switched. Brendan Gregg discusses Off-CPU analysis. Combining on-CPU time, measured with a performance
counter, with off-CPU time will give wall clock time. Linux perf 5.20 adds a command line option to ''perf record'' to gather off-CPU data.

P¶

PEBS¶

Intel Processor Event-Based Sampling (PEBS) is a hardware mechanism that enables precise performance profiling by capturing specific processor events and their associated instruction pointers. Unlike traditional sampling methods that rely on periodic interrupts, PEBS allows developers to collect performance data with minimal overhead and pinpoint performance bottlenecks with high accuracy. When a predefined event occurs, such as a cache miss or branch misprediction, PEBS records the instruction pointer and other relevant information in a dedicated buffer. This data can then be analyzed to identify performance hotspots and optimize code for improved efficiency. PEBS is a powerful tool for software developers and performance analysts seeking to understand and optimize application performance on Intel processors.

perf.data¶

By default output from various perf commands is stored in a file named perf.data.

perf-event¶

A kernel abstraction used to reference data being gathered about a particular kind of kernel event.

perf-evlist¶

See man1/perf-evlist.1.

Pinned Event¶

Pinned events are scheduled at a higher priority to flexible events. If they can't be scheduled within the kernel they don't multiplex and enter an error state.

PMU¶

A Performance Monitoring Unit is a device within the Linux kernel that the perf tool interacts with initially through the perf_event_open system call.

Precise Event¶

When sampling an interrupt is triggered and the sample gathered in the kernel. There is typically a delay between the interrupt and the sample, leading the accuracy of the sample to be limited and skid. CPU extensions like PEBS, IBS and SPE can be used to reduce this. Placing the modifier 'p' after an event modifies its precision/skid:

SAMPLE_IP can have arbitrary skid
'p' -SAMPLE_IP must have constant skid
'pp' - SAMPLE_IP requested to have 0 skid
'ppp' -SAMPLE_IP must have 0 skid, or uses randomization to avoid sample shadowing effects.

Q¶

QPI¶

Intel Quick Path Interconnect.

R¶

RAT¶

In modern CPUs, a Resource Allocation Table (RAT) is a structure that renames architectural registers to a larger set of physical registers during the out-of-order execution process. This renaming breaks false dependencies caused by register naming limitations, allowing instructions to execute in parallel and boosting performance. The RAT also tracks which physical registers hold the results of in-flight instructions, ensuring that data is used at the correct time.

ROB¶

Reorder Buffer, tracks in-flight instructions and their results in out-of-order CPUs.

RS¶

Reservation Station, buffers instructions awaiting resources (functional units, data) before execution.

S¶

SDF¶

Scalable Data Fabric.

Skid¶

The distance between where a sample is, an instruction, and where the sampling event was actually triggered. Ideally there would be no skid on samples.

SLC¶

System Level Cache generally used interchangeably with Last Level Cache but may incorporate caches outside of the processor.

SMI¶

System Management Interrupts trasition the CPU into System Management Mode to hanle high privilege events.

SMM¶

On x86 generally System Management Mode, on ARM Secure Monitor Mode, is a highly privileged firmware/BIOS code.

SMT¶

Simultaneous multithreading.

Software Event¶

They are kernel/os-based low-level counters. To identify the list of supported software events use the command: perf list software

SPE¶

ARM's Statistical Profiling Extension is an optional ARM v8 feature that provides precise sampling. Currently the feature is common on server ARM CPUs.

sysfs¶

A filesystem for exporting kernel objects.

T¶

TAD¶

Last-Level cache Tag-and-data Units on Marvell CN10K family silicon.

TLB¶

TLB stands for Translation Lookaside Buffer. It is a specialized cache that stores the recent translations, via the page table, of virtual memory addresses to physical memory addresses.

TPEBS¶

Timed Process Event Based Sampling on newer Intel processors adds retirement latency information to samples. The retirement latency is the number of cycles between the sampled and the previous instructions retiring. One use is to avoid having hard coded constants in top-down analysis metrics, so that overheads are more reflective of the actual workload.

TOR¶

The Table-of-Requests (TOR) is a data structure within Intel's Integrated Memory Controller (IMC) that stores and tracks in-flight memory requests made by CPU cores.

Task¶

Kernel term for a process (if just 1 thread) or thread.

TSX¶

Principally an Intel term, Transactional Synchronization Extensions

U¶

Uncore¶

Functions of the microprocessor not in the core.

UOp¶

Abbreviation for micro-operation commonly used by Intel.

UPI¶

Intel Ultra Path Interconnect.

V¶

VMA¶

Virtual Memory Area used by the kernel to manage process memory.

X¶

xGMI¶

eXternal GMI link is a socket-to-socket interconnect that is part of AMD's Infinity Fabric.